Project Overview | System Overview | Significant Milestones | Tools used During Design | Development and Testing | Problems and Tradeoffs
Project Overview:
The goal of this project is to determine more frequency synthesizer circuit options, and the objectives to complete this goal are determined by the following:
• Survey existing literature on fractional phase lock techniques
• Compile a summary of pros and cons of each design
• Select one of the topologies for use in a field programmable array (FPGA) and glue logic
• Simulate the topology chosen using an FPGA
• Test the system using printed circuit board with user interface
The Project:
Our project is to design of a factional phase locked loop phase detector using an FPGA and VHDL design language. This phase locked loops are a means to synthesize a sinusoidal signal at a desired radio frequency (RF) that is locked in phase to a crystal reference. This type of device is used extensively in the communication industry such as cell phones. This provides a stable RF that may be tuned in frequency to allow communication channel to be selected.
The project would involve the design of a fractional phase detector in which our team would have to study techniques for fractional division. Our team would be required to research various means of factional division used in the industry and develop VHDL code to implement a fractional divider to be used in the final chosen phase detector topology. A working oscillator design and printed circuit board will be provided to integrate with the chosen design for testing.
Synopsis of Design Requirements:
Our team will perform a survey of existing literature on fractional phase lock techniques and compile a summary of what they have found including the pros and cons of each design. Then a given topology will be selected for implementation in the FPGA, a plan for functional division between firmware (FPGA) and hardware (glue logic) will be developed. A component level hardware design shall be completed with schematics for the PCB implementation. The FPGA firmware will be designed and simulated. Then a printed circuit board will be fabricated for the design and assembled, firmware will be loaded on the target hardware for operational verification and debugging conducted. For testing a human input to the FPGA will include a port for loading firmware and an RS-232 port for loading the desired frequency of operation via a personal computer.