Project Overview | System Overview | Significant Milestones | Tools used During Design | Development and Testing | Problems and Tradeoffs
Problems and Tradeoffs:
Wulfsberg PLL CircuitOur team ran into some trouble when we received our VCO, Change pump and Loop filter from our client. Seeing that the components were attached to a PCB board it made it very difficult to use without high noise issues. Even if it was possible to attach the FPGA to wulfbergs PLL circuit, the device would bring a lot of noise into the equation because we are working at such high frequencies.
After realize this we developed two of our own systems to build and test. The first system we began to develop has a frequency range of 200 – 400 MHz as our client has requested. We picked out a VCO, a passive filter, TCXO, Oscillator driver, and a Schmitt trigger for converting the sine wave output to a digital square wave. However, the FPGA implementation of the PFD doesn’t have a fast enough response time for the circuit to operate at the required frequency along with other issues that have a risen. Below is the summery of the issues our team encountered:
FPGA:
The FPGA was not received until 1 month after scheduled date of receipt. FPGA's are not able to handle the frequency range specified by our client. We then had to scale the frequency range down to what an FPGA can handle.
VCO:
Our VCO received from client 2 months after desired date, putting project behind schedule. VCO received from client was already integrated with a PLL, team did not use it due to concerns of noise issues when attempting to bypass integrated PLL IC.
Filter:
The client wanted team to use filter built into same board as VCO, which already had a PLL IC built in. team chose not to use the board from the client due to concerns of noise issues when attempting to bypass integrated PLL IC, as well as concerns that any actions taken by the team to bypass the PLL would end up destroying the board, with no chance of a replacement.
Charge Pump:
The matched MOSFET IC's difficult to find. the matched MOSFET IC's the team did find tied the body connections together, which stopped the team from being able to make a cascaded current mirror charge pump, this delayed the completion of the charge pump.
Divider:
Team believed that divider needed 50% duty cycle output from the divider, delaying its completion by approximately 1 month. Team found high latency issues when building the divider, due to the delays inherent to the logic elements in an FPGA. The team initially believed another divider design to work excellently in simulation, until the simulation was changed to look at a timing simulation. This 2nd design proved infeasible after studying the results of the timing simulation.
Phase Frequency Detector:
Team found the divider had caused a phase shift between the divided signal and the crystal reference. When the project was scaled back, this proved to not cause as much of an issue.
Interface:
The team attempted to build a serial interface using VHDL. While simulation seemed to prove the serial interface had been designed correctly, physical testing of the RS-232 interface proved otherwise.
